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The key to realizing a high-performance frequency-modulated continuous wave (FMCW) laser frequency-sweeping light source is how to extend the frequency-swept bandwidth and eliminate the effect of nonlinearity. To solve these issues, this paper designs a broadband high-linear FMCW frequency-sweeping light source system based on the combination of fixed temperature control and digital optoelectronic phase-locked loop (PLL), which controls the temperatures of the two lasers separately and attempts to achieve the coarse spectral stitching based on a time-division multiplexing scheme. Furthermore, we uses the PLL to correct the frequency error more specifically after the coarse stitching, which achieves the spectrum fine stitching and, meanwhile, realizes the nonlinearity correction. The experimental results show that our scheme can successfully achieve bandwidth expansion and nonlinearity correction, and the sweeping bandwidth is twice as much as that of the original single laser. The full-width half-maximum (FWHM) of the FMCW output is reduced from 150 kHz to 6.1 kHz, which exhibits excellent nonlinear correction performance. The relative error of the FMCW ranging system based on this frequency-swept light source is also reduced from 1.628% to 0.673%. Therefore, our frequency-swept light source with excellent performance has a promising application in the FMCW laser ranging system. [ABSTRACT FROM AUTHOR]

A low-power clock and data recovery circuit with a quarter rate operating at 10 GHz is presented. This circuit consists of a phase lock loop and an input data retiming circuit. The phase-locked loop includes an LC oscillator, a quarter-rate detector, a charge pump, and a low-pass filter. The output of the oscillator is applied to a two-bit counter, so the clock frequency is reduced to 2.5 GHz with eight different phases which applied to the phase detector to sample the input data in different phases. Each sampling is done in 12.5 picoseconds. The innovative application of this two-bit counter eliminates the requirement of the multiphase oscillator, thus helps to reduce overall power dissipation. The power consumption of the voltage control oscillator is about 5.83 mW. In addition, reducing the clock frequency improves the performance of the phase detector circuit. The total power dissipation of the proposed CDR is evaluated to be 10.9 mW from a 1.8 V supply. [ABSTRACT FROM AUTHOR]

Copyright of Power Generation Technology is the property of Power Generation Technology Editorial Office and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This paper deals with the phase noise affecting communication systems, where local oscillators are employed to obtain reference signals for carrier and timing synchronizations. The most common discrete-time phase noise channel model is analyzed, with the aim to fill the gap between measurements and analytical models. In particular, the power loss and the intersymbol interference due to the presence of phase noise is evaluated with reference to the measurements parameters and to the system bandwidth. Moreover, the impact on the communication systems’ performance of the phase noise originating from the oscillator non-idealities is considered, in case of free-running and phase-locked oscillators. The proposed analysis allows to extrapolate useful information about the performance of practical systems by investigating the power spectral density of the oscillator phase noise. An expression for the variance of the residual phase error after tracking, which depends on the main parameters of practical oscillators, is derived, and used to study the dependence of the performance on the symbol rate.

The purpose of this paper is to propose a novel technique for extracting the position signal from an inductive displacement transducer named a linear variable differential transformer (LVDT). In general, the movement of the LVDT core causes its primary inductance change in linear form. The primary winding of the LVDT is used as a time-dependent element for the triangular and square wave generator, which can be called self-oscillation, to generate frequency. The advantage of the proposed technique is that it can measure the displacement using the LVDT without an external oscillator. The change in primary inductance causes the frequency deviation generated by the oscillator. The deviated frequency is captured and converted into a voltage signal using the principle of the phase-locked loop. All the components used in this study are commercially available. The merits of this proposed technique are simple configuration, small size, and low cost. Moreover, the operating range of the LVDT can be extended without the limitation of the nonlinear transfer characteristic. The performance of the proposed technique is discussed in detail and confirmed by experimental implementation. Experimental results show that the maximum error from the proposed technique is about 0.42% and the operating range of the LVDT can be extended to more than 200%. It can be seen that the proposed technique is suitable for embedded measurement in small or micro robots. [ABSTRACT FROM AUTHOR]

This paper presents a single-step automatic tuning procedure and an estimator of key parameters of the drill-string system used in deep drilling applications. It is aimed at precise tuning of an external vibration suppression system based on speed control loop of the drilling electrical drive tuned for "stiff" motor-side speed control (the so-called speed source behavior), and the external drill-string torque feedback used for torsional vibration active damping. The automatic tuning procedure is carried out for the case when the drill-string and drill-bit are hoisted from the bottom of the well and the drilling electrical drive briefly enters the limit cycle oscillatory behavior under stiff speed control. The proposed auto-tuning system features a suitable control-oriented process model of the torsional oscillator and a modified-mixer phase detector phase locked-loop equipped with adaptive second-order generalized integrator (band-pass filter) for the extraction of key features of the drive resonance mode. The overall control system design relies on the so-called damping optimum criterion which guarantees a desired level of closed-loop system damping. The functionality of the proposed adaptive control system with automatic tuning of the control strategy has been systematically verified by means of comprehensive simulations, and the effectiveness of the drill-string parameter estimator has also been confirmed using the previously recorded field data to illustrate its robustness in the presence of realistic measurement noise. [ABSTRACT FROM AUTHOR]

This paper presents a wideband approach for L5 and S-band integer-N phase-locked loop (PLL) targeting Indian Regional Navigation Satellite System (IRNSS) applications. A reference spur reduction technique using a G m − C filter is proposed. The reference spur is improved by 7 dB when compared with one without any G m − C filter. The wideband integer-N PLL is designed and fabricated in UMC 65-nm CMOS process. The G m − C filter block consumes 200 μ A current. The wideband voltage-controlled oscillator (VCO) oscillates from 1.6 GHz to 3.2 GHz having a tuning range (TR) of 40 % , achieving a best and worst phase noise of ≈−122 dBc/Hz and ≈ − 116 dBc/Hz at a 1 MHz offset, respectively. [ABSTRACT FROM AUTHOR]

A digital phase-locked loop (DPLL) based on sliding window infinite Fourier transform (SWIFT) and αSWIFT is proposed to extract the vibration and velocity parameters from the phase-modulated carrier signal. The phase of a carrier signal gets modulated when it is reflected from a vibration object due to the Doppler effect. Therefore, the phase-modulated carrier signal contains the Doppler signal that has the vibration information. The SWIFT or αSWIFT structure is designed from sliding discrete-time Fourier transform (DTFT) where the exponential window provides higher weightage to recent samples. It acts as a phase detector in the proposed DPLL, and its bandwidth can be varied based on the values of the time-constant. A controller unit, along with a bi-quad oscillator, is introduced in the proposed DPLL structure to remove any leakages in the system and to synchronize the system units in the parameter estimation. The proposed scheme is implemented in MATLAB/SIMULINK environment and validation for real-time applications is done using dSPACE 1202 MicrolabBox. [ABSTRACT FROM AUTHOR]

The single-phase three-leg unified power quality conditioner (UPQC) can achieve the functions of voltage compensation, reactive power compensation, and harmonic compensation. However, traditional control algorithms require a phase-locked loop to obtain the real-time phase angle of the grid voltage, which undoubtedly increases algorithm complexity. To simplify the phase-locked calculation, this paper proposes a control method without the phase-locked loop for the single-phase three-leg UPQC. In the proposed scheme, the instantaneous value of the grid voltage is employed to realize the grid integration control. Then, the load voltage reference is calculated in real time using a second-order generalized integrator. Moreover, a simple algorithm for reactive power and harmonic compensation is discussed, further simplifying the control algorithm. Finally, a small-scale experimental platform is built, and the effectiveness of the proposed method is verified by the experimental results. [ABSTRACT FROM AUTHOR]

In order to realize the generality of wind turbines hardware in the loop platform, a universal wind turbines hardware in the loop experiment platform is built to realize the optimal control of wind turbines. In view of the problem that direct drive wind turbines can affect the normal operation of direct drive wind turbines when the power grid voltage is unbalanced or asymmetrical, this study adopts the algorithm based on the decoupling of positive sequence current and negative sequence current to eliminate the negative sequence current and keep the constant output power. By inhibiting the double frequency fluctuation of the reactive power of the wind turbines when the fault occurs, the reference value of the active power and reactive power is 0, the amplitude of the double frequency fluctuation component of the grid reactive power is 0, and the purpose of eliminating the negative sequence current and making the output of the wind turbines stable is achieved. The simulation verification is carried out on the experimental platform. The experimental results show that the active power output of wind turbines remains unchanged and the grid-connection adaptability of wind turbines is significantly improved, which verifies the rationality and effectiveness of the method. [ABSTRACT FROM AUTHOR]

In recent years, several research works have addressed and developed the phase-locked loop (PLL) in single-phase grid-connected converters with different structures and properties. Each has merits and demerits, such as a complex structure, high computational burden, and slow transient response. This paper aims to comprehensively review advanced single-phase PLLs based on transport delay operators to realize signal orthogonality. A deep insight into the PLLs' small-signal modeling, main characteristics, stability analysis, and loop filter design are provided in this paper. The main advantages and drawbacks are explained for each type of PLL in terms of different performance indexes, such as settling time, estimation error, and ripples in the estimated grid information. This paper also aims to provide optimal tuning and design of the loop filter gains from the large-signal model point of view, including all the nonlinearities, adopting the stochastic optimization method. All simulations are implemented using the MATLAB/Simulink 2018b environment to validate all theoretical analyses of this paper. The sampling and nominal frequencies are set to be 100 kHz and 50 Hz throughout all the simulation studies. [ABSTRACT FROM AUTHOR]

Summary In this study, an improved anti‐windup proportional‐integral predictive direct power control strategy with a phase‐locked loop (PLL) is proposed and applied to a three‐level shunt active power filter (SAPF) neutral point clamped (NPC) inverter using space vector modulation (SVM) technique. The SAPF has to ensure sinusoidal waveforms and unity power factor in the grid side, by eliminating harmonic currents and compensating reactive power of the nonlinear loads. Active and reactive powers as well as the DC bus voltage controls are performed using anti‐windup proportional and integral actions with a predictive algorithm, without a need for an exhaustive mathematical model. The control law is modulated using the SVM technique allowing fixed switching frequency and low power ripples. The performances of the suggested control have been verified through an electronic STM32F407 card under diverse and severe conditions. The obtained results confirmed the expected objectives in terms of current and voltage quality, robustness, and dynamic response. [ABSTRACT FROM AUTHOR]

In this study, a method for controlling the repetition frequency of a mid-infrared ultrashort pulse laser with a central wavelength of 2.8 µm is developed. A ring cavity that is insensitive to the polarization state of the laser light emitted from the fiber end was constructed to stabilize the oscillation of the mid-infrared ultrashort pulse laser. More oscillation conditions for the ultrashort pulse laser based on nonlinear polarization rotation are found than the conventional method. To confirm that the pulse oscillation is mode-locked, ultrashort pulse oscillation was confirmed by an autocorrelator. The pulse repetition frequency of this robust ultrashort pulse laser was controlled. The control method was based on the phase-locked loop (PLL) control. A wedge window was inserted into the cavity and mounted on a linear stage driven by a piezoelectric transducer. By driving the piezoelectric transducer, the position of the wedge window changed, and the resulting optical path length also changed. The repetition frequency was controlled based on this principle. Optical path length control by the wedge window and temperature control provides an Allan deviation of approximately 1 mHz. [ABSTRACT FROM AUTHOR]

Synchronization units are vital for the stable operation of grid-tied converters in generation and transmission. There are two main synchronization units, i.e., phase-locked loop (PLL) and power synchronization controller (PSC), with the corresponding drawbacks in weak and strong grid respectively. Recently, the hybrid synchronization controller (HSC) is proposed in order to make up the deficiencies of PLL and PSC in weak and strong grid respectively. This paper deduces the detailed impedance characteristics of PSC and HSC and compares their cons and pros to show the stability mechanism of HSC. Moreover, two types of HSCs are also presented and compared in this article with slight difference in structure. It is found that the impedance of Type II based HSC has smaller amplitude and better phase margin than PSC around fundamental frequency, while Type I based HSC has larger amplitude and less phase margin than PSC. Type II based HSC can improve the stability and Type I based HSC can worsen the stability compared with PSC. Realtime experiments are carried out to verify this.

Summary: The time delay unit‐based PLLs (TD‐PLLs) are widely used in grid synchronization in single‐phase power systems. However, the TD‐PLL is vulnerable to frequency variations and harmonic disturbances, leading to grid synchronization failures. Analysis shows that the performance degradation is due to the inability to obtain the variation of the input signal frequency. This paper proposes a new time delay‐based phase‐locked loop called immune to double frequency component TD‐PLL (IDFC‐TD‐PLL) based on a feedback structure to accurately capture the variation of input signal frequency, which can improve the dynamic performance and the performance against harmonic interference. Simulations and experiments have evaluated the performance of the proposed phase‐locked loop, demonstrating its superior accuracy and dynamic performance compared to the phase‐locked loops referred in the paper. [ABSTRACT FROM AUTHOR]

A single-phase binary/quadrature phase-shift keying (BPSK/QPSK) demodulator basing on a phase-locked loop (PLL) is described. The demodulator relies on a linear characteristic a rising-edge RESET/SET flipflop (RSFF) employed as a phase detector. The phase controller takes the average output from the RSFF and performs a sub-ranging/re-scaling operation to provide an input signal to a voltage-controlled oscillator (VCO). The demodulator is truly modular which theoretically can be extended for a multiple-PSK (m-PSK) signal. Symbol-error rate analysis has also been extensively carried out. The proposed BPSK and QPSK demodulators have been fabricated in a 0.18 μm digital complementary metal–oxide– semiconductor (CMOS) process where they operate from a single supply of 1.8 V. At a carrier frequency of 60 MHz, the BPSK and QPSK demodulators achieved maximum symbol rates of 25 and 12.5 Msymb/s while consuming 0.68 and 0.79 mW, respectively. At these maximum symbol rates, the BPSK and QPSK demodulators deliver symbol-error rates less than 7.9×10-10 and 9.8×10-10, respectively where their corresponding energy per bit figures were at 27.2 and 31.7 pJ. [ABSTRACT FROM AUTHOR]

A single-phase/single-loop multiple-phase-shift-keying (m-PSK) demodulator is described. The demodulator relies on a linear range of an exclusive-OR (XOR) gate employed as a phase detector. The phase controller takes the average output from the XOR gate and performs a sub-ranging/re-scaling operation to provide an input signal to a voltage-controlled oscillator (VCO). The demodulator is truly modular which theoretically can be extended for an m-PSK signal. The proposed single-phase binary-/quadrature-PSK (BPSK/QPSK) demodulators have been implemented with low-cost discrete components. The core of the phase controller simply relies on number of stages of a full-wave rectifier and a linear amplifier built from well-known op-amp-based negative feedback circuits. The demodulator prototypes operate from a single supply of 5 V. At a carrier frequency of 100 kHz, both the BPSK and QPSK demodulators achieved the maximum symbol rate of 20 ksymbol/s respectively. At these symbol rates, the BPSK and QPSK demodulators deliver symbol-error rates less than 2×10-10 and 7×10-10. [ABSTRACT FROM AUTHOR]

A low-power and low-jitter 1.2 GHz Integer-N PLL (INPLL) is designed in a 65 nm standard CMOS process. A novel high-gain sampling phase detector (PD), which takes advantage of a transconductance (Gm) cell to boost the gain, is developed to increase the phase detection gain by ~100× compared to the Phase-Frequency Detectors (PFDs) used in conventional PLLs. Using this high detection gain, the noise contribution of the PFD and Charge Pump (CP), reference clock, and dividers on the PLL output is minimized, enabling low output jitter at low power, even when using low-frequency reference clocks. To provide a sufficient frequency locking range, an auxiliary frequency-locked loop (AFLL) is embedded within the INPLL. An integrated Lock Detector (LD) helps detect the INPLL locked state and disables the AFLL to save on power consumption and minimize its impact on the INPLL jitter. The proposed INPLL layout measures 700 µm × 350 µm, consumes 350 µW, and exhibits an integrated phase noise (IPN) of −37 dBc (from 10 kHz to 10 MHz), equivalent to 2.9 ps rms jitter, while keeping the spur level 64 dBc lower, resulting in jitter figure of Merit ( F o M j i t t e r ) ~−236 dB. [ABSTRACT FROM AUTHOR]

This paper proposes a phase-locked loop (PLL) with a low bandwidth and high estimation performance in terms of position and speed through speed feedforward compensation for driving extended back electromotive force (EEMF)-based sensorless control for an interior permanent magnet synchronous motor (IPMSM). In this case, lowering the bandwidth to reduce sensitivity to disturbances of the PI controller, where the position error is controlled to zero, may create a problem of decreased estimation performance. The proposed method calculates speed through mathematical calculations of the EEMF, which is observed using an EEMF-based IPMSM model, and adds it to the output of the PLL. The added speed feedforward compensation reduces the computational burden of the PI controller. Therefore, fast estimation dynamic characteristics can be obtained even at low bandwidths. The improvement of the estimation performance of the proposed method is evaluated by analyzing the equivalent block diagram using the final value theorem theory. Through this, the estimation performance is shown. It can be seen that the position estimation error for various types of speed inputs converges to zero. In addition, validity and implementation of this method are verified by experimental results. [ABSTRACT FROM AUTHOR]

The phase frequency detector (PFD) is an important component in a phase-locked loop (PLL). PFD detects the timing difference between the reference clock (REFCK) and the feedback clock (FBCK). PFD plays a major role in deciding the amount of time required by a PLL to achieve lock. The blind zone in the PFD causes inaccurate PFD output. This negatively impacts the PLL's lock-in time. The increase in lock-in time poses great challenges for developing high-speed PLLs. This paper proposes a PFD architecture that eliminates the reset pulse when the timing difference between the REFCK and the FBCK is significantly high. The elimination of the reset pulse in this way leads to a blind zone free PFD across process, voltage, and temperature (PVT) variations. The PFD is realized and implemented in the Cadence spectre environment using the UMC 0.18 μ m CMOS process. From the results, it can be stated that the designed PFD is blind zone free across PVT variations. The proposed PFD-based PLL locks faster than the traditional PFD-based PLL. The proposed PFD consumes 163 μ W power at a 100 MHz operating frequency which is the lowest compared to the earlier reported works. Its operational range is [ - 2 π , 2 π ]. The PFD occupies an area of 0.0069 mm 2 . The proposed design is well suited to low-power, high-speed PLL applications. [ABSTRACT FROM AUTHOR]

Copyright of Electric Power Engineering Technology is the property of Editorial Department of Electric Power Engineering Technology and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

In this study, a 94 GHz PLL chip was designed using the integer-N PLL structure, and the results of a high-temperature test for the chip are discussed. The 94 GHz PLL was designed to exhibit a phase noise of −90 dBc/Hz or less at a 1 MHz offset frequency using a 0.13 μm SiGe BiCMOS process. In addition, a high-temperature test of the MIL-STD-331C standard was conducted on a manufactured 94 GHz SiGe PLL chip mounted on a test board. As a result of the test, the chip total current change before and after the high-temperature test was 4.7 %, and the phase noise changes of both 94 GHz VCO and PLL were 2.3 dB. These results confirm that, even after the high-temperature test, the flattening of the low-frequency noise was well maintained because the VCO noise was filtered by the PLL. [ABSTRACT FROM AUTHOR]

The single-phase three-leg unified power quality conditioner (UPQC) can achieve the functions of voltage compensation, reactive power compensation, and harmonic compensation. However, traditional control algorithms require a phase-locked loop to obtain the real-time phase angle of the grid voltage, which undoubtedly increases algorithm complexity. To simplify the phase-locked calculation, this paper proposes a control method without the phase-locked loop for the single-phase three-leg UPQC. In the proposed scheme, the instantaneous value of the grid voltage is employed to realize the grid integration control. Then, the load voltage reference is calculated in real time using a second-order generalized integrator. Moreover, a simple algorithm for reactive power and harmonic compensation is discussed, further simplifying the control algorithm. Finally, a small-scale experimental platform is built, and the effectiveness of the proposed method is verified by the experimental results.

Abstract Frequency‐adaptive prefilters are widely used in the phase‐locked loop (PLL) to suppress input disturbances. However, the parameters of the PLL and prefilters are often designed separately or based on an inaccurate model. The positive feedback effect introduced by the frequency adaption (FA) is usually ignored, leading to non‐optimal performance. Based on the accurate small‐signal model with a particular focus on the FA, this paper proposes an optimal design method for these advanced PLLs. The PLL based on dual second‐order generalized integrator (DSOGI) is taken as an example to demonstrate the principle. With different gain margins, the optimal damping factors of DSOGI and PLL, as well as the natural frequency of PLL, are obtained using the proposed method. Then the global optimal parameters are obtained by evaluating the settling time and overshoot. The analysis shows that the truly optimal parameters are quite different with those provided in the literature, and the dynamic performance is significantly enhanced without degrading the steady‐state performance. Experimental results are presented to verify the theoretical analysis.

The key to realizing a high-performance frequency-modulated continuous wave (FMCW) laser frequency-sweeping light source is how to extend the frequency-swept bandwidth and eliminate the effect of nonlinearity. To solve these issues, this paper designs a broadband high-linear FMCW frequency-sweeping light source system based on the combination of fixed temperature control and digital optoelectronic phase-locked loop (PLL), which controls the temperatures of the two lasers separately and attempts to achieve the coarse spectral stitching based on a time-division multiplexing scheme. Furthermore, we uses the PLL to correct the frequency error more specifically after the coarse stitching, which achieves the spectrum fine stitching and, meanwhile, realizes the nonlinearity correction. The experimental results show that our scheme can successfully achieve bandwidth expansion and nonlinearity correction, and the sweeping bandwidth is twice as much as that of the original single laser. The full-width half-maximum (FWHM) of the FMCW output is reduced from 150 kHz to 6.1 kHz, which exhibits excellent nonlinear correction performance. The relative error of the FMCW ranging system based on this frequency-swept light source is also reduced from 1.628% to 0.673%. Therefore, our frequency-swept light source with excellent performance has a promising application in the FMCW laser ranging system.

The precise calculation of phase angle, voltage magnitude and frequency is crucial for the effective control of power electronic inverters connected to an electrical power system. The phase-locked loop (PLL) is a commonly employed method for measuring these variables. Nevertheless, the reliability of this measurement is influenced by transient events in the electrical power system and varies depending on the nature of the event and the specific design of the PLL. Notably, PLLs utilizing the double second-order generalized integrator are widely adopted for power converter synchronization purposes. This article proposes a three-phase PLL, which is based on the single-phase version previously reported by the authors. The proposed PLL, based on an alternative integrator approach, allows a fine adjustment of the tolerance to disturbances in the input voltage thanks to a second feedback gain in its pre-filter. It is reasonable to anticipate that the three-phase PLL will exhibit similar strengths to the single-phase version; however, in the three-phase case, an additional integrator is involved in pre-filtering the quadrature signals, and the double integrator is not employed as the quadrature signal generator. The performance of the proposed PLL is assessed by comparing it to other PLLs based on the second-order integrator, using a processor-in-the-loop approach. [ABSTRACT FROM AUTHOR]

This paper presents the novel islanding detection technique that depends on the piezoelectric sensors for distributed generation sources (DGs) in the grid-integrated operation mode. The islanding detection method employs a piezoelectric sensor for the detection of the frequency variations during grid disruptions. The designed diaphragm-based sensor has a natural frequency as that of the fundamental frequency of the system frequency signal. Any further deviations from the natural frequency due to the disturbances will be sensed by the sensor and a control signal is being sent to the associated circuit breaker for suitable action. The sensor structure is modeled using the finite element method and implemented in the Phase-Locked Loop (PLL) of the grid-integrated DGs. The proposed circular diaphragm-based sensor structure will have the bandwidth in the range of natural frequency with the tolerance rate of ±1% and uses the input signal received from the PLL controller outer loop. The proposed islanding detection technique's performance and reliability for grid-integrated DG are validated using the real-time hardware in the loop test-bed platform. The HIL virtual simulated responses show that the method can be proposed effectively for islanding detection in the event of frequency variations in the grid-integrated DG systems. [ABSTRACT FROM AUTHOR]

Featured Application: This paper proposes virtual admittance feedforward compensation and phase correction for average-current-mode-controlled totem-pole PFC converters. It can effectively reduce total harmonic distortion (THD) and improve the power factor (PF) of the converter. The proposed control strategy can be directly used in on-board chargers (OBCs) for electric vehicles, power supplies for server clusters, communication equipment, industrial equipment, etc. This paper explores a current distortion problem in totem-pole bridgeless power factor correction (PFC) converters with average current mode (ACM) control. With in-depth modeling for the current and voltage loops, it was found that the current distortion is caused by the limited current loop bandwidth and input filter capacitor. These factors lead to the presence of a susceptance component in the input admittance, which degrades the power factor (PF) and total harmonic distortion (THD) of the PFC converter. To solve this problem, this paper proposes virtual admittance feedforward compensation (VAFC) and phase correction methods to adjust the input admittance to pure conductance. The VAFC can generate virtual admittance that compensates for susceptance components in the input admittance, while phase correction can generate an equivalent current source that offsets the current in input capacitors. Furthermore, a phase lock loop (PLL) is introduced to realize the VAFC, which reduces the feedforward interference caused by input voltage sampling noise. Finally, an experimental prototype was built to verify the effectiveness of the proposed strategies. According to the test results, the proposed compensation strategy improves the PF by 1.23%, while reducing the THD by 2.52% and achieving a peak efficiency of 98.69%. [ABSTRACT FROM AUTHOR]

Within the framework of the development of the theory of hidden oscillations, the problem of determining the boundary of global stability and revealing its hidden parts corresponding to the nonlocal birth of hidden oscillations is considered. For a phase-locked loop with a proportional-integrating filter and a piecewise-linear phase detector characteristic, effective methods for determining bifurcations of global stability loss, for obtaining analytical formulas for bifurcation values, and for constructing trivial and hidden parts of the global stability boundary are suggested. [ABSTRACT FROM AUTHOR]

Copyright of Electronic Components & Materials is the property of Electronic Components & Materials and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This paper analyzes the performance requirements that need to be met by a clock generator applied to a low-temperature quantum computer and analyzes the negative effects on the clock generator circuit under low-temperature conditions. In order to meet the performance requirements proposed in this paper and suppress the negative effects brought about by the low temperature, a clock generator for ultra-low-temperature quantum computing is designed. This clock generator is designed by using F-CLASS Voltage Controlled Oscillator (VCO), power filter, tail resistor, differential charge pump, and other techniques. And the noise characteristics of the clock generator are analyzed by Impulse Sensitive Function (ISF) and simulation results. After simulation tests, the average power consumption of the clock generator designed in this paper is 7 mW, the phase noise is −121 dBc/Hz@1 MHz, and the jitter is 62 fs. The performance of the clock generator meets the performance requirements proposed in this paper, and the reduction in the corner frequency proves that the circuit will have better performance at low temperatures. [ABSTRACT FROM AUTHOR]

Background: Heterodyne interferometry offers an exciting solution for achieving sub-nanometer or ten-picometer-order mechanical displacement measurements because of its high resolution and noise immunity. Objective: In this paper, we investigate the stability and resolution of a conventional displacement-measuring heterodyne interferometer using a single phase-locked loop (PLL) at a sub-nanometer or 10-pm level over an µm-scale measurement regime in normal air. Methods: In the experiment, we perform the beat frequency reduction of the heterodyne signals to take advantage of a low-cost frequency sampling data acquisition (DAQ). The primary calculations of the single phase-locked loop (PLL) algorithm are implemented in a point-by-point (pt-pt) construction, providing pt–pt low-pass filters (LPFs) with high noise suppression. The output is appended into an array of N points and averaged to reduce the noise of the outgoing signal again. Using the PLL phase meter with the beat frequency reduction can ensure a mdeg-order phase measurement with Allan deviation stability of ~ 10 µdeg over 1000 s. We consider a combination of the miniaturization of optical paths in air and the PLL phase meter integrated with low-cost devices while ensuring mdeg-order measurement stability to achieve the interferometer's pm-order measurement resolution and stability. Results: The measurement results show that the interferometer can achieve a resolution of 26 pm over a 5 μm-range mechanical displacement measurement. The Allan deviation stability of the interferometer reaches ~ 10 pm over a sampling time of 30 s, and the displacement noise floor is 10 pm/Hz1/2 above 1 Hz. Conclusions: The new signal-processing PLL phase meter provides higher noise reduction than the old one presented in our previous work. With low cost but high resolution and stability, the PLL phase meter is incredibly suitable for pm-order displacement-measuring heterodyne interferometry. Combining a well-reduced PLL phase meter and a conventional heterodyne interferometer with a stable, isolated configuration and the minimization of optical paths in the air can give the measurement system a high resolution and stability. The measurement system can have a more significantly improved resolution of a few tens of pm than interferometers presented in previous publications and stability comparable to the modified heterodyne interferometers shown in earlier works over the sampling time of 30 s (possibly up to 100 s). A conventional heterodyne interferometer with a single PLL is expected to perform large-range displacement measurements with resolution at ten picometer levels in air. [ABSTRACT FROM AUTHOR]

Objectives: Real time precise point positioning(RT-PPP) technology can realize one-way timing with sub-nanosecond precision and daily stability of 1×10-14 level. Clock steering affects the stability of the receiver's output time-frequency signal, however, inappropriate clock steering parameters can degrade the short-term stability of the receiver's oscillator. Methods: To combine the short-term stability of the oscillator and the long-term stability of the RT-PPP, we propose a phase-locked loop clock steering model for the RT-PPP time-frequency receiver. The noises of the system are analyzed. And the parameter design method of the second-order phase-locked loop is proposed. Experiments were carried out with the clock steering model and designed parameters used in the RT-PPP time-frequency receiver. Results: Experimental results show that the frequency stability of the RT-PPP time-frequency receiver is 4.344 4×10-12 at 1 s, 1.102 9×10-14 at 1 d, the frequency stability of the time intervals shorter than 300 s can get close to the free-running Rubidium clock, the frequency stability of the time intervals longer than 300 s can get close to the RT-PPP. Conclusions: The proposed clock steering model and parameter design method can well realize the combination of the oscillator's short-term stability and the RT-PPP's long-term stability. [ABSTRACT FROM AUTHOR]

The proposed work delivers a robust control solution for a single-phase permanent magnet synchronous generator-based wind power conversion system (PMSG-WPCS) to enhance grid integration capability. The proposed control approach also offers an extended facility to fulfill low-voltage fault ride-through (LVRT) requirements under adverse grid conditions. Unlike the conventional observer-based PLL (O-PLL) approach, the proposed improved Lyapunov theory-based prefilter (ILP) is helpful in yielding a quadrature signal to solve the single-phase grid synchronization problem. Moreover, the proposed prefilter can leverage delayed signal operation, which improves the harmonic and the DC-offset component rejection abilities while eliminating the need for internal feedback-based submodule blocks for the case of an O-PLL. Consequently, the proposed ILP-PLL exhibits better dynamic behavior to rapidly synchronize a grid-tied power converter and can accurately track the fundamental amplitude information that is required for inverter control to meet the fault ride-through requirements. In addition, the suggested LVRT controller ensures smooth transition between the unity and non-unity power factor modes for superior converter control over reactive current injection into the grid to recover the grid from faults while maintaining a lower amount of total harmonic current distortions. The dynamic performance of the proposed control scheme is experimentally validated in view of the existing O-PLL approach for lower-rating wind-turbine-based PMSG-WPCS. [ABSTRACT FROM AUTHOR]

Frequency‐adaptive prefilters are widely used in the phase‐locked loop (PLL) to suppress input disturbances. However, the parameters of the PLL and prefilters are often designed separately or based on an inaccurate model. The positive feedback effect introduced by the frequency adaption (FA) is usually ignored, leading to non‐optimal performance. Based on the accurate small‐signal model with a particular focus on the FA, this paper proposes an optimal design method for these advanced PLLs. The PLL based on dual second‐order generalized integrator (DSOGI) is taken as an example to demonstrate the principle. With different gain margins, the optimal damping factors of DSOGI and PLL, as well as the natural frequency of PLL, are obtained using the proposed method. Then the global optimal parameters are obtained by evaluating the settling time and overshoot. The analysis shows that the truly optimal parameters are quite different with those provided in the literature, and the dynamic performance is significantly enhanced without degrading the steady‐state performance. Experimental results are presented to verify the theoretical analysis. [ABSTRACT FROM AUTHOR]